Highly integrated Dynamic Random Access Memory (DRAM) devices such as 256 MB DRAMs and gigabit DRAMs can be constructed due to technological advances that have enabled increases in storage capacity. To manufacture a highly integrated DRAM, a variety of memory cell layouts satisfying a design rule have been proposed. Generally, a preferable memory cell layout contains characteristics such as mask friendliness and photolithography friendliness. A memory cell transistor fabricated using the desirable memory cell layout is expected to have high electrical performance. Mask friendliness is attained if limitations of mask manufacturing process are met, writing time is shortened and mask fidelity is satisfied. The photolithography friendliness can be attained if an optical process is corrected with a single-pitch layout.
Conventional layouts of active regions of a memory cell include a layout of straight active regions and a layout of diagonal active regions. U.S. Pat. Nos. 5,194,752, 5,305,252 and 6,031,262 disclose the layout of diagonal active regions.
FIG. 1A shows the conventional layout of straight active regions 1 on a wafer. FIG. 1B is a plan view of a mask pattern for forming the conventional layout of straight active regions shown in FIG. 1A. FIG. 1C is a plan view of active regions AR1 and word lines WL1. The active regions AR1 are printed on the wafer using the mask pattern shown in FIG. 1B. FIG. 2A shows the conventional layout of diagonal active regions 2. FIG. 2B is a plan view of a mask pattern for forming the conventional layout of diagonal active regions shown in FIG. 2A. FIG. 2C is a plan view of active regions AR2 and word lines WL2. The active regions AR2 are printed on the wafer using the mask pattern shown in FIG. 2B.
Referring to FIG. 1B, the mask pattern for forming the straight active regions AR1 shown in FIG. 1C requires a plurality of auxiliary patterns 1b, 1c, 1d and 1e with different sizes. The auxiliary patterns 1b, 1c, 1d and 1e are disposed adjacent to a main pattern 1a. The auxiliary patterns 1b, 1c, 1d and 1e are used for optical corrections. Referring to FIG. 2B, the mask pattern for forming the diagonal active regions AR2 shown in FIG. 2C includes at least twelve rectangular patterns 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2j, 2k and 2l. The twelve rectangular patterns 2a to 2l define one active region. It is known that the mask patterns shown in FIGS. 1B and 2B are difficult to fabricate and have low mask fidelity. Further it takes a long time to fabricate the mask patterns, and photolithography using the mask patterns has a low process margin.
With the conventional layout of straight active regions, two word lines WL1 intersect each active region AR1 as shown in FIG. 1C to form memory cell pairs. That is, a memory cell pair is formed in each active region AR1. The word lines WL1 cross the edge of the active regions AR1. The width of the edge of the active region AR1 is narrower than the width of the center of the active region AR1 because the edge of the active region AR1 is more affected by an optical proximity effect than the center of the active region AR1. Thus, an actual gate width GW1 of a memory cell transistor is narrower than the width of the active region AR1.
With the conventional layout of diagonal active regions two word lines WL2 intersect each active region AR2 as shown in FIG. 2C to form memory cell pairs. The word lines WL2 cross the active regions AR2 diagonally. As a result, the whole intersection of the word line WL2 and the active region AR2 cannot be used as an actual gate region. Only a portion indicated by a shaded area A can be used as the actual gate region. Accordingly, an actual gate width GW2 is narrower than the width of the active region AR2. As the actual gate width decreases, the threshold voltage Vth of the memory cell transistor decreases. The decreased threshold voltage increases sub-threshold leakage current, and deteriorates dynamic refresh characteristic of DRAMs. In FIGS. 1C and 2C, GL1 and GL2 represent gate lengths.